Design of Low-Power Pipelined Multipliers with Various Output Precision
碩士 === 國立中山大學 === 資訊工程學系研究所 === 94 === With the emergence of portable computing and communication systems, power consumption has become one of the major objectives during VLSI design. Furthermore, multipliers are always fundamental building blocks and the bottleneck in terms of power consumption in...
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ndltd-TW-094NSYS53920502016-05-27T04:18:10Z http://ndltd.ncl.edu.tw/handle/45323958809154636794 Design of Low-Power Pipelined Multipliers with Various Output Precision 可變輸出精確度之低功率管線化乘法器設計與實現 Yuan-chih Chuang 莊淵智 碩士 國立中山大學 資訊工程學系研究所 94 With the emergence of portable computing and communication systems, power consumption has become one of the major objectives during VLSI design. Furthermore, multipliers are always fundamental building blocks and the bottleneck in terms of power consumption in many DSP and multimedia applications. Therefore, it is crucial to minimize the power consumption of multipliers in the system for low-power VLSI design. Besides, energy-efficient multiplier is greatly desirable for DSP systems and computer architectures. In many of these systems, the dynamic-range of input operands for multiplier is usually very small. In addition, the least significant bits of output products are often rounded or truncated to avoid growth in word size. Based on these features, this thesis presents an approach to design low-power and reconfigurable signed pipelined multipliers. The approach dynamically detects input range of the multiplier and disables the switching operations of non-effective ranges to decrease the power consumption. Moreover, the proposed approach can reconfigure the output precision of the multiplier to save power consumption. We apply this approach to two architectures: array-based and Booth-based architecture. Experimental results show that the proposed array-based pipelined multiplier leads to up 47% power saving and Booth-based multiplier leads to up 30% power saving with a little additional area and delay overheads. Besides, in order to accord with the low cost and high profit-making goal of systematic products and shorten construction period, we have designed a low-power multiplier generator. User could use the user interface to configure the multiplier size, low power architecture and the precision that user need. The generator will create the hardware architecture of low-power multiplier automatically. Shiann-Rong Kuang 鄺獻榮 2006 學位論文 ; thesis 83 en_US |
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碩士 === 國立中山大學 === 資訊工程學系研究所 === 94 === With the emergence of portable computing and communication systems, power consumption has become one of the major objectives during VLSI design. Furthermore, multipliers are always fundamental building blocks and the bottleneck in terms of power consumption in many DSP and multimedia applications. Therefore, it is crucial to minimize the power consumption of multipliers in the system for low-power VLSI design. Besides, energy-efficient multiplier is greatly desirable for DSP systems and computer architectures. In many of these systems, the dynamic-range of input operands for multiplier is usually very small. In addition, the least significant bits of output products are often rounded or truncated to avoid growth in word size.
Based on these features, this thesis presents an approach to design low-power and reconfigurable signed pipelined multipliers. The approach dynamically detects input range of the multiplier and disables the switching operations of non-effective ranges to decrease the power consumption. Moreover, the proposed approach can reconfigure the output precision of the multiplier to save power consumption.
We apply this approach to two architectures: array-based and Booth-based architecture. Experimental results show that the proposed array-based pipelined multiplier leads to up 47% power saving and Booth-based multiplier leads to up 30% power saving with a little additional area and delay overheads.
Besides, in order to accord with the low cost and high profit-making goal of systematic products and shorten construction period, we have designed a low-power multiplier generator. User could use the user interface to configure the multiplier size, low power architecture and the precision that user need. The generator will create the hardware architecture of low-power multiplier automatically.
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author2 |
Shiann-Rong Kuang |
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Shiann-Rong Kuang Yuan-chih Chuang 莊淵智 |
author |
Yuan-chih Chuang 莊淵智 |
spellingShingle |
Yuan-chih Chuang 莊淵智 Design of Low-Power Pipelined Multipliers with Various Output Precision |
author_sort |
Yuan-chih Chuang |
title |
Design of Low-Power Pipelined Multipliers with Various Output Precision |
title_short |
Design of Low-Power Pipelined Multipliers with Various Output Precision |
title_full |
Design of Low-Power Pipelined Multipliers with Various Output Precision |
title_fullStr |
Design of Low-Power Pipelined Multipliers with Various Output Precision |
title_full_unstemmed |
Design of Low-Power Pipelined Multipliers with Various Output Precision |
title_sort |
design of low-power pipelined multipliers with various output precision |
publishDate |
2006 |
url |
http://ndltd.ncl.edu.tw/handle/45323958809154636794 |
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