Implementation and performance evaluation of DVB-H baseband receiver
碩士 === 國立中山大學 === 通訊工程研究所 === 94 === In this thesis, the baseband signal processing and hardware implementation of the Digital Video Broadcasting - Handheld (DVB-H) are investigated. DVB-H is an emerging and promising wireless communication system and is based on the Orthogonal Frequency Division Mu...
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ndltd-TW-094NSYS56500192016-05-27T04:18:11Z http://ndltd.ncl.edu.tw/handle/38817656963035295631 Implementation and performance evaluation of DVB-H baseband receiver DVB-H基頻接收機實現及效能評估 Wei-jun Wu 吳偉俊 碩士 國立中山大學 通訊工程研究所 94 In this thesis, the baseband signal processing and hardware implementation of the Digital Video Broadcasting - Handheld (DVB-H) are investigated. DVB-H is an emerging and promising wireless communication system and is based on the Orthogonal Frequency Division Multiplexing (OFDM) scheme. The algorithms for baseband signal processing include timing synchronization, frequency offset compensation, channel estimation, and scatter pilot detection. The developed algorithms are verified using Matlab program to meet performance requirements. Then, the algorithms are implemented using Verilog hardware description language (HDL), which is downloaded to Xilinx FPGA (Field Programmable Gate Array) for system verification. The selected algorithms for baseband signal processing have to meet the both the requirements of system performance and low complexity. Chih-Peng Li 李志鵬 2006 學位論文 ; thesis 85 zh-TW |
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碩士 === 國立中山大學 === 通訊工程研究所 === 94 === In this thesis, the baseband signal processing and hardware implementation of the Digital Video Broadcasting - Handheld (DVB-H) are investigated. DVB-H is an emerging and promising wireless communication system and is based on the Orthogonal Frequency Division Multiplexing (OFDM) scheme. The algorithms for baseband signal processing include timing synchronization, frequency offset compensation, channel estimation, and scatter pilot detection. The developed algorithms are verified using Matlab program to meet performance requirements. Then, the algorithms are implemented using Verilog hardware description language (HDL), which is downloaded to Xilinx FPGA (Field Programmable Gate Array) for system verification. The selected algorithms for baseband signal processing have to meet the both the requirements of system performance and low complexity.
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Chih-Peng Li |
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Chih-Peng Li Wei-jun Wu 吳偉俊 |
author |
Wei-jun Wu 吳偉俊 |
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Wei-jun Wu 吳偉俊 Implementation and performance evaluation of DVB-H baseband receiver |
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Wei-jun Wu |
title |
Implementation and performance evaluation of DVB-H baseband receiver |
title_short |
Implementation and performance evaluation of DVB-H baseband receiver |
title_full |
Implementation and performance evaluation of DVB-H baseband receiver |
title_fullStr |
Implementation and performance evaluation of DVB-H baseband receiver |
title_full_unstemmed |
Implementation and performance evaluation of DVB-H baseband receiver |
title_sort |
implementation and performance evaluation of dvb-h baseband receiver |
publishDate |
2006 |
url |
http://ndltd.ncl.edu.tw/handle/38817656963035295631 |
work_keys_str_mv |
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