Compilers for IXP Network Processor

碩士 === 國立清華大學 === 資訊工程學系 === 94 === As huge improvement of internet infrastructure in the recent decade, people gain much more convenience on those high-speed communication and data transformation from internet than in 90’s. Network processor is a new computer architecture which is designed for nowa...

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Main Authors: Chih-Hsiang Huang, 黃智翔
Other Authors: Jenq-Kuen Lee
Format: Others
Language:en_US
Published: 2006
Online Access:http://ndltd.ncl.edu.tw/handle/95709694671820685805
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spelling ndltd-TW-094NTHU53920932015-12-16T04:39:23Z http://ndltd.ncl.edu.tw/handle/95709694671820685805 Compilers for IXP Network Processor 網路交換處理器之爪哇編譯器 Chih-Hsiang Huang 黃智翔 碩士 國立清華大學 資訊工程學系 94 As huge improvement of internet infrastructure in the recent decade, people gain much more convenience on those high-speed communication and data transformation from internet than in 90’s. Network processor is a new computer architecture which is designed for nowadays high throughput network data processing, which is mainly composed of a core-processor and multiple co-processors with hierarchical memory system. This kind of complex system communicates with variety of memory architecture could make packet processing jobs separated to different mutual exclusive ones and processed by each computing units synchronously and as fast as possible. Each computing unit is supposed to run a component, which we call it PPF (packet processing function) in a packet processing flow to make sure every packet is processed in an efficient way. Intel’s network processor (Internet eXchange Processor, IXP) is the perfect example allows a single stream packet/cell processing problem to be integrated into multiple, sequential, and synchronous tasks that can be linked together easily. It has one XScale processor and multiple RISC processors called “micro-engines” which allows network application processed in simultaneous methods. Network applications shall be separated in several different tasks. In this paper, we bring up a solution using the approaches to emphasize on enabling Java programming languages over IXP network processors to make a good model for compilers over multi-core architectures. Previous work about multi-core compilers over IXP is the IXA Software Development Kit which supports only C front-end and must be tuned by human efforts. In this paper, I propose a neat interface for users to program Intel IXP network processors without considering about hardware details. Also, by the convenience of GNU Compiler Collection, programmers on Intel IXP could easily use this tools to help program the network application on IXP. Jenq-Kuen Lee 李政崑 2006 學位論文 ; thesis 56 en_US
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description 碩士 === 國立清華大學 === 資訊工程學系 === 94 === As huge improvement of internet infrastructure in the recent decade, people gain much more convenience on those high-speed communication and data transformation from internet than in 90’s. Network processor is a new computer architecture which is designed for nowadays high throughput network data processing, which is mainly composed of a core-processor and multiple co-processors with hierarchical memory system. This kind of complex system communicates with variety of memory architecture could make packet processing jobs separated to different mutual exclusive ones and processed by each computing units synchronously and as fast as possible. Each computing unit is supposed to run a component, which we call it PPF (packet processing function) in a packet processing flow to make sure every packet is processed in an efficient way. Intel’s network processor (Internet eXchange Processor, IXP) is the perfect example allows a single stream packet/cell processing problem to be integrated into multiple, sequential, and synchronous tasks that can be linked together easily. It has one XScale processor and multiple RISC processors called “micro-engines” which allows network application processed in simultaneous methods. Network applications shall be separated in several different tasks. In this paper, we bring up a solution using the approaches to emphasize on enabling Java programming languages over IXP network processors to make a good model for compilers over multi-core architectures. Previous work about multi-core compilers over IXP is the IXA Software Development Kit which supports only C front-end and must be tuned by human efforts. In this paper, I propose a neat interface for users to program Intel IXP network processors without considering about hardware details. Also, by the convenience of GNU Compiler Collection, programmers on Intel IXP could easily use this tools to help program the network application on IXP.
author2 Jenq-Kuen Lee
author_facet Jenq-Kuen Lee
Chih-Hsiang Huang
黃智翔
author Chih-Hsiang Huang
黃智翔
spellingShingle Chih-Hsiang Huang
黃智翔
Compilers for IXP Network Processor
author_sort Chih-Hsiang Huang
title Compilers for IXP Network Processor
title_short Compilers for IXP Network Processor
title_full Compilers for IXP Network Processor
title_fullStr Compilers for IXP Network Processor
title_full_unstemmed Compilers for IXP Network Processor
title_sort compilers for ixp network processor
publishDate 2006
url http://ndltd.ncl.edu.tw/handle/95709694671820685805
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