A 5GHz CMOS RF Front-end with Dynamic Matching for Wireless LAN Application

• Main Authors: Chen-Jung Chuang, 莊振榮
• Other Authors: Jenn-Chyou Bor
• Format: Others
• Language: en_US
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/81158468379765011818

碩士 === 國立清華大學 === 電機工程學系 === 94 === The thesis proposes the design and implementation of a single-chip CMOS RF front-end circuit for IEEE802.11a WLAN application. For SOC implementation, the use of Zero-IF receiver architecture reduces the necessity of off-chip component such as IF filter and IF circuit. At the same time, the interference of the image signal is avoided. The RF front-end circuit is composed of three blocks, differential low noise amplifier (LNA), active down-conversion mixer and poly phase filter. In addition, a constant-gm bias circuit and a digital control circuit are built in. The digital control circuit not only controls the operation band selection of low noise amplifier for wide-band application but compensates the process variation for higher chip yield. The use of double-balance active Gilbert mixer at I/Q path provides higher conversion gain and needs lower local oscillation signal amplitude. Finally, a poly phase filter is used to generate quadrature signal for I/Q path. The whole RF front-end circuit is a wide-band design with digital control mechanism. The overall noise figure is 9dB and S11 is below -10dB within the 5.25 ~ 5.85 GHz band. The conversion gain of the system is 22.9dB, P1dB is -27.5dBm and IIP3 is -12.5dBm. The RF front-end circuit is implemented in 0.18um 1P6M CMOS process and operated with 1.8V power supply. In addition, it consumes 19.67mW (buffers consume 33.3mW) and occupies 0.980 * 1.396 mm2 die area including bond pads.