High Fault Coverage Built In Self Test for PLLs

• Main Authors: Chien-Han Lin, 林建翰
• Other Authors: Tsin-Yuan Chang
• Format: Others
• Language: en_US
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/46685730762423297089

碩士 === 國立清華大學 === 電機工程學系 === 94 === ABSTRACT This thesis proposes a method for phase-locked loop detection. PLL plays a very important role in communication systems in present times, such as low-jitter PLL-based frequency synthesizer、clock recovery and synchronization. For the PLL, to improve the yield and achieve cost reduction, it is important to detect the faulty block when it does not meet the specifications as expected. Unlike in the domain of digital IC testing, where structural test methods such as scan-tests and build-in self testing (BIST) have become a common practice, testing of mixed-signal ICs in a structured way is still in its infancy. Thus is, an effective built-in self test (BIST) structure of a PLL in digital applications is presented in this thesis. In this thesis, a BIST approach is presented for locating structural fault model in PLL blocks including VCO, Divider-By-N block, Loop Filter, Phase Detector and Charge-Pump. By applying exiting elements of PLLs to test and measure, the proposed BIST circuit that is verified by the simulation in a 0.18um CMOS process has the advantages of small area overhead and 99.72% fault coverage.