High Fault Coverage Built In Self Test for PLLs
碩士 === 國立清華大學 === 電機工程學系 === 94 === ABSTRACT This thesis proposes a method for phase-locked loop detection. PLL plays a very important role in communication systems in present times, such as low-jitter PLL-based frequency synthesizer、clock recovery and synchronization. For the PLL, to improve the yi...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/46685730762423297089 |