Design and Analysis of H.264 Intra-Prediction and Mode-Decision Architecture Using Rate-Distortion Optimization

• Main Authors: Wei-Gen Wu, 吳煒根
• Other Authors: Yung-Chang Chen
• Format: Others
• Language: en_US
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/85601283766231713841

碩士 === 國立清華大學 === 電機工程學系 === 94 === H.264/AVC is the latest video compression standard. It concentrates on video compression and robust transmission support over networks. H.264/AVC could achieve about 60% bit-rate saving over MPEG-2, and about 40% bit-rate saving over MPEG-4 at the same video quality. Because of its high compression efficiency, H.264 attracts high interest for many applications such as High Definition DVD, Digital TV, Digital Camcorders, Camera Phone, Internet video streaming, and others. However, H.264’s complicated encoding process cannot guarantee real-time coding implementation. Therefore, how to design a high efficient intra coder operating in real time is one of the most important things in the H.264 intra encoding issue. In this thesis, we propose two designs of H.264 intra frame coding circuit. In these two designs, nine Intra4x4, four Intr16x16 prediction modes for luminance samples and four Intra_chroma prediction modes for chrominance samples are implemented. In the first design for simple applications, we propose a new architecture of intra prediction generator to support most prediction modes except Intra16x16 plane mode and we also propose a simple way to implement Intra16x16 plane mode. The predictor can produce two pixels on average in every cycle. When these two predictors are combined with an arrangement of “fun_unit_buffer” in different modes, all the prediction modes in 4x4MB can be produced in at most five cycles. In this design, we also propose to solve the problem that the neighboring pixels from previous 4x4 MB cannot be reconstructed in time by reordering the prediction mode selections. Fortunately, because the prediction orders in Intra16x16 mode are after the orders in all Intra4x4 modes, we can use two 16x16 MB buffers as MB pipeline between prediction part and CAVLC part to store the 16x16 residual data for better mode and current mode as long as the entropy coding is fast enough. In this way, we can save the clock cycles required by reconstructing the best modes in Intra4x4 or Intra16x16 modes. In the second design for high performance applications, we use the architecture of the first design in this thesis but add the rate distortion optimization part. We calculate the total bits needed by mode information and residual data to get high compression performance. We propose an efficient and fast way to calculate the bits needed by the residual data, which are the critical part in the design. The rate estimation would cause the mode decision path longer. Therefore, we also propose a way to change the 4x4MB prediction order in the 16x16 MB and reorder the mode selections, so that we can solve the long waiting time problem. The prototype design is implemented using Xilinx multimedia board and the design limitation is 100MHz in the worst case, which is higher than the required frequency, 49MHz, in 720x480 size frame.