| Summary: | 碩士 === 國立臺灣大學 === 土木工程學研究所 === 94 === This research introduces two ways to implement a matrix solver on FPGA: one way is to design a hardware solver with VHDL, the other to develop a embedded solver system by programming soft core processor MicroBlaze. To utilize parallel advantage of FPGA, we design a pipeline architecture according to the parallelism of Jacobi Iteration, and discuss the computing complexity and limits on parallelism of the sequential algorithm Gauss-Jordan Elimination. We adopt serial handshake protocols for matrix data I/O, where a terminal program on PC transmit data through RS232 port and receive data returned by FPGA. We implement the sequential algorithm on both hardware solver and embedded solver system. Both solvers can solve a 32bit float number matrix of free dimension, with computing time correspond with the complexity of order n3. With limited on-board RAM, the max matrix dimension we can exam in this study is 63 on hardware solver, which takes 16.15ms for solving, and 50 on embedded solver system, which takes 0.18s for solving. This study successfully provides two solutions to solve matrix without CPU. The hardware solver shows better computing performance, and the embedded solver system takes shorter development process. Although we do not exam our parallel architecture for the iterative algorithm, it is hope that the task can be achieved in the future with proper RAM module planning.
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