| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 94 === As wirelsss communication technology advances, related applications are becoming pervasive; however, the major communication resource, bandwidth, is limited and needs to be utilized efficiently. Cognitive radio is considered a promising solution for spectrum utilization dilemma. A cognitive radio can sense the surrounding changes and adjust its transmission parameters such as bandwidth, power and modulation properly to obtain better performance and resource utilization. Currently, one major research direction is to construct cognitive radios onto existing primary systems to realize advantages mentioned above.
In this thesis, we aim to design and implement a baseband cognitive radio receiver chip above the platform of IEEE 802.11a, resulting no interference to existing users inside. Under the entire cognitive radio project in NTU sponsored by MediaTek Inc., this thesis defines firstly 4 main cognitive features that should be integrated into our baseband system and constructs the baseband receiver based on discussion about IEEE 802.11a MAC. To provide dynamic spectrum allocation ability, we adopt a dedicate sequence as long preamble with good correlation and power properties that conventional OFDM system cannot compete with. By designing system packet format and channel model appropriately, the chip is fully compatible with IEEE 802.11a. An improved algorithm for doing signal to noise ratio estimation is used to get faster environmental awareness; also, the receiver has basic sensing capability. Through parameterized design, an overall of 128 operating configuration is achieved, enabling receiver more performance diversity and functioning fully as an 802.11a mobile terminal. Finally, the baseband cognitive radio receiver chip is implemented by TSMC 0.18um 1P6M CMOS process, with an area of 3.584x3.585mm2. Post-layout simulation shows the chip consumes 720mW under 1.8V supply voltage and 160MHz clock rate, supporting data rate up to 1.404Gbps. Also, superior performance of the chip and desired capability are confirmed through the comparison between post-layout and software simulations.
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