| Summary: | 碩士 === 國立臺灣大學 === 電信工程學研究所 === 94 === Researches on the broadband power amplifier for microwave wide band system and frequency divider for phase locked loops are presented in this dissertation.
Power amplifier is an essential building block in transmitter system. Broadband power amplifier is not easy to design. Using distributed amplifier as the architecture can achieve wide band. Two broadband Pas are designed and implemented, and they achieve broadband, high gain, medium power and gain flatness.
A 4-37GHz broadband power amplifier using 0.15μm has been design and fabricated. The circuit cascades two distributed power amplifier for higher output power. The other is a 15-50GHz broadband power amplifier. This circuit cascade two distributed amplifier and a single-stage amplifier as the output. Reducing the stage of the distributed amplifier and using interstage matching network can reduce the dc power consumption and achieves flat gain.
Phase-locked loop (PLL) technique has been developed for decades and is the most frequently adopted to realize a high-quality LO source. Frequency divider is the design bottleneck for high frequency PLL since the conventional flip-flop based structure is not suitable for high-speed operation. In this thesis, high speed frequency divider topologies, such as injection locked frequency divider and regenerative frequency divider are investigated.
A 30-GHz divided-by-four frequency divider fabricated using TSMC 0.18-μm CMOS has been designed and fabricated. The circuit adopts current-reuse method to reduce dc power and size of the layout due to less components needed. A 50-GHz divided-by-four frequency divider fabricated using TSMC 0.18μm CMOS. Using matching networks, these circuits achieve divide-by-four function directly with the small chip size.
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