A platform-based HW/SW co-design for FPGA: Using JPEG compression as an example
碩士 === 國立臺灣大學 === 電機工程學研究所 === 94 === Aiming to a mixed software/hardware system, in this thesis, we make use of the platform-based methodology to design hardware accelerators on FPGAs. We focused on reducing the hardware/software communication overheads in partitioning the codes. We design three ki...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/86893481023524367444 |
| Summary: | 碩士 === 國立臺灣大學 === 電機工程學研究所 === 94 === Aiming to a mixed software/hardware system, in this thesis, we make use of the platform-based methodology to design hardware accelerators on FPGAs. We focused on reducing the hardware/software communication overheads in partitioning the codes. We design three kinds of hardware accelerators on FPGAs and discuss how to measure communication costs. The result of the measurement is then used to divide the codes in a hardware/software that enhances the performances of software. Finally we analyze the performances of our designs.
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