A platform-based HW/SW co-design for FPGA: Using JPEG compression as an example
碩士 === 國立臺灣大學 === 電機工程學研究所 === 94 === Aiming to a mixed software/hardware system, in this thesis, we make use of the platform-based methodology to design hardware accelerators on FPGAs. We focused on reducing the hardware/software communication overheads in partitioning the codes. We design three ki...
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2006
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ndltd-TW-094NTU054420532015-12-16T04:38:21Z http://ndltd.ncl.edu.tw/handle/86893481023524367444 A platform-based HW/SW co-design for FPGA: Using JPEG compression as an example 基於平台的FPGA軟硬體共同設計︰以JPEG壓縮為例 Chin Feng Tsai 蔡青峰 碩士 國立臺灣大學 電機工程學研究所 94 Aiming to a mixed software/hardware system, in this thesis, we make use of the platform-based methodology to design hardware accelerators on FPGAs. We focused on reducing the hardware/software communication overheads in partitioning the codes. We design three kinds of hardware accelerators on FPGAs and discuss how to measure communication costs. The result of the measurement is then used to divide the codes in a hardware/software that enhances the performances of software. Finally we analyze the performances of our designs. 王勝德 2006 學位論文 ; thesis 47 zh-TW |
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碩士 === 國立臺灣大學 === 電機工程學研究所 === 94 === Aiming to a mixed software/hardware system, in this thesis, we make use of the platform-based methodology to design hardware accelerators on FPGAs. We focused on reducing the hardware/software communication overheads in partitioning the codes. We design three kinds of hardware accelerators on FPGAs and discuss how to measure communication costs. The result of the measurement is then used to divide the codes in a hardware/software that enhances the performances of software. Finally we analyze the performances of our designs.
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| author2 |
王勝德 |
| author_facet |
王勝德 Chin Feng Tsai 蔡青峰 |
| author |
Chin Feng Tsai 蔡青峰 |
| spellingShingle |
Chin Feng Tsai 蔡青峰 A platform-based HW/SW co-design for FPGA: Using JPEG compression as an example |
| author_sort |
Chin Feng Tsai |
| title |
A platform-based HW/SW co-design for FPGA: Using JPEG compression as an example |
| title_short |
A platform-based HW/SW co-design for FPGA: Using JPEG compression as an example |
| title_full |
A platform-based HW/SW co-design for FPGA: Using JPEG compression as an example |
| title_fullStr |
A platform-based HW/SW co-design for FPGA: Using JPEG compression as an example |
| title_full_unstemmed |
A platform-based HW/SW co-design for FPGA: Using JPEG compression as an example |
| title_sort |
platform-based hw/sw co-design for fpga: using jpeg compression as an example |
| publishDate |
2006 |
| url |
http://ndltd.ncl.edu.tw/handle/86893481023524367444 |
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