Sigma-Delta Modulation Class-D Dgital Power Amplifier
碩士 === 國立臺灣科技大學 === 電子工程系 === 93 === A Class D power amplifier by sigma-delta modulation (SDM) is proposed. Cycle-by-cycle control loop is adopted in converting the analog signal into a digital one. Except a constant pulse time to detect the sampled input signal level, a duty period is generated by...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/89847845166835096545 |
| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 93 === A Class D power amplifier by sigma-delta modulation (SDM) is proposed. Cycle-by-cycle control loop is adopted in converting the analog signal into a digital one. Except a constant pulse time to detect the sampled input signal level, a duty period is generated by a discharging/charging rate generated in SDM and its length is dependent on the detected input level and is a multiple of the constant sampling pulse time. Signal process and system model for converting the analog signal into digital one through the SDM modulator is explored. A prototype of 100W class D power amplifier is examined for assessing the theoretical investigation and practicality. The power efficiency is over 87%. The total harmonic distortion (THD) measured without EMI filter is less than 4%.
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