| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 93 === This research presents a high resolution Time-to-Digital Converter. In order to eliminate the influence of the element mismatch and the temperature variation, the phase-locked loops circuit is used to produce stable system clock. The separate time digitizer improves the time resolution by interpolating within the clock period. The interpolator is based on analog dual-slope conversion. Furthermore, the trigger voltage controlled oscillator is utilized to make start pulse synchronous with system clock. It could reduce one interpolator and has the improvement in cost.
The Time-to-Digital Converter with 25-ps resolution and had been integrated in 0.35-μm standard 2P4M CMOS technology. The size of this chip, not including pads, is 875-μm * 420-μm. According to simulation results, the integral nonlinearity is 0.8LSB and the conversion time is within 204.8-ns.
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