Design of a Bus Controller for a SOPC-based Microprocessor

• Main Authors: Wei-cheng Hung, 洪偉程
• Other Authors: Chen-mie Wu
• Format: Others
• Language: zh-TW
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/43642922897191880530

碩士 === 國立臺灣科技大學 === 電子工程系 === 94 === This thesis is related to the design and implementation of an on-chip system bus for a SOPC-based embedded system. The research work in this thesis consists of three parts. The first part is about the design of the specification for an on-chip system bus. The second part is about the design and implementation of on-chip memories and peripherals which are connected to the system bus through their bus interfaces. The third part is about the design and implementation of a JTAG-based testing system with build-in self-test capability. As a whole, this thesis is related to the development of an on-chip system bus with build-in self-test capability for embedded systems.