| Summary: | 碩士 === 東海大學 === 數學系 === 94 === This research is the continuation of a special kind of studies about the on-site flow-control technique of WIP scatteration in IC fabrication. It is different from those designs developed by the traditional production planning and managing framework. Maintaining the original spirit of evenly scattering WIP’s in workstations, we provide a new and efficient method called the previous-time method for wafer dispatching, and simulates related data to prove the advantages. Moreover, we introduce the concept of storage in order to fix the tag machine dispatching problem caused by past studies. As to the flow-control technique which is not evenly maintaining WIP scatteration in every workstation, we provide a dispatching design called the accelerating method for IC fabrication to bottleneck area. We also point out it’s applied condition, which is different from that under the previous-time method above. The study is done by Mr. Hsi Fu-nan and I. We share the same results of the study but branch out in writing up the theses. Mr. Hsi focuses on the new storage design and the accelerating method for dispatching, and I concentrated on the motivation and executing the previous-time method for wafer dispatching.
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