Application of Simulated Annealing for Semiconductor Batch Process Scheduling With Bicriteria

• Main Authors: Jian-Ming Li, 李建鳴
• Other Authors: Yu-Tuen Chang
• Format: Others
• Language: zh-TW
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/2j859h

碩士 === 國立臺北科技大學 === 工業工程與管理系所 === 94 === To improve the reliability of semiconductor products, burn-in operations is essential in the final testing processes. While the time needed at burn-in operation is much more than the other ones, it makes burn-in operations the bottleneck of the procedure in final test. This study is aimed at burn-in operations characterized batch processing. Dynamic arrival of jobs with due date, non-identical job size, batch processing time as the longest processing among all jobs in a batch, and limitation on the sum of job sizes in a batch are considered. Procedure of simulated annealing to minimize makespan and total tardiness of jobs on a single batch-processing machine is proposed in the study. GRLPT, R1, and R2 heuristic algorithms in literature, in which jobs size is assumed identical, are modified as GRLPT_S, R1_S and R2_S in this study to accommodate job sizes in a batch. Various experiments were conducted to compare the proposed method with those modified algorithms. The computational results show that the proposed algorithm performs quite well as GRLPT_S, R1_S and R2_S on the criterion of makespan, while the proposed algorithm improves the criterion of total tardiness by 5.2 percent average.