Design of Digital Control Wide Range Frequency Synthesizer

• Main Authors: Pei-Ju Lin, 林貝儒
• Other Authors: Yuh-Shyan Hwang
• Format: Others
• Language: zh-TW
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/x6a86e

碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 94 === For a modern communication system, a precise frequency is necessary. The PLL (phase-locked loop) technique has been developed for many years. This dissertation focuses on the design of wide range PLL and frequency synthesizer. The proposed circuit includes a phase frequency detector, a charge pump, a loop filter, a voltage controlled oscillator, and a frequency divider. The PFD can detect the difference of two signals and generate a wide charge or discharge pulse signal for the charge pump to generate a controlling voltage. It will be no more start-up problem when we use the charge pump with matched current and make the complete circuit can depress the generation of noise efficiently. The loop filter is composed by a second-order RC circuit and is capable to filtrate the high frequency part of the charge pump. The VCO provide the digital controlling selections of frequency. The whole circuit provides a fast tune, accurate, and wide range frequency synthesizer. The proposed wide range frequency synthesizer was designed in TSMC 0.35um CMOS process with supply voltage 3.3V. The applied frequency range is able to operate in 10MHz~100MHz for the input frequency and 100MHz ~ 600MHz for the output frequency. The power consumption is 6.8463mW. The total layout area is 1.2 * 1.2mm2.