Dummy-Beta-Latency-Free Turbo Decoder Design

• Main Authors: Ling-Fan Yen, 葉凌帆
• Other Authors: Wen-Ta Lee
• Format: Others
• Language: zh-TW
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/w7zuys

碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 94 === Turbo code is a forward error correct code which has good error correction capability and near Shannon limiting performance. Traditional turbo decoder needs large memory size and has long decoding latency for implementation. This paper presents a dummy-beta-latency-free algorithm which can reduce the decoding latency of sliding window from 4L to 1L. In hardware implementation, we can use a dummy-beta memory unit to replace one backward calculation unit and two SISO sub-memories. Experimental results show that our architecture can save 27%~45% memory bit and 65%~68% memory area. Then, we have verified this algorithm using Xilinx FPGA (HW-V4-ML402-USA) system. Finally, a dummy-beta-latency-free turbo decoder is designed using TSMC 0.18μm 1P6M CMOS technology. The chip occupies 1.9mm 1.9mm and has a clock frequency of 104.1Mbps.