Multi-Outputs Fractional-N Frequency Synthesizer for SoC Use

• Main Authors: Ching-Wen Kuo, 郭敬文
• Other Authors: Kuo-Hsing Cheng
• Format: Others
• Language: en_US
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/84193162983804787451

碩士 === 淡江大學 === 電機工程學系碩士在職專班 === 94 === Beside to overcome the complex bus data transformation, the most challenges of SoC design still need to provide precise clock signals and power trails for each internal block to make sure the whole system can working well. In a multi-functions single ship design, the generating of necessary clock signals always accompanies higher power consumption, more noises, and bigger layout area for passive components. Usually, these drawbacks can only be solved by modifying block diagram and circuit structure. We focus on studying a new frequency synthesizer structure to meet the SoC design clock requirements and try to overcome the power consumption issue, area problem, and the complexity of clock tree routing in using traditional frequency synthesizer for SoC design. The using of multi-phases clocks that output from a phase-locked loop to be inputs of pseudo fractional-N divider can generate multi-clocks without multiple relationships. These frequency independent clocks can satisfy complex demands of SoC design. In this thesis, presented algorithm can exactly find required VCO stage number and frequency. Another target of proposed algorithm is to minimize required phase-locked loop number. Two major circuit blocks are modified for performance improving. The first modified block is the programmable divider with EOC Detecting and Reloading Algorithm functions. This divider is an integer divider which connects one of VCO outputs with PFD to perform a programmable phase-locked loop. The detect circuit of this divider is simplified and the latency of its reload signal is optimized for improving bandwidth. These modifications make the divider can working between 1MHz to 3.5GHz. The high frequency dead-lock issue is also fixed. The second modified block is the output stage dividers that connect behind VCO. This block is called as Pseudo Fractional-N Divider. It is one of the most important sub circuits in this frequency synthesizer. This pseudo fractional-N divider uses selected VCO output phases as its inputs for combining final SoC clocks. The pseudo fractional-N divider can help to cancel the frequency dependence of VCO and final SoC clocks. With lot of other advantages, the pseudo fractional-N divider can synchronize output clocks, make output phases and duty programmable, and improve output jitters. This paper presents a new frequency synthesizer structure to simplify clock tree in complex SoC design. The improving of power consumption, layout area, and programming ability drives SoC design to a higher flexibility for IPs integration. The proposed frequency synthesizer can be use as an embedded sub block in SoC design or an independent discrete IP for system implementation. Only mature circuit blocks are used to composing circuit modules, thus it forces the SoC design to have more possibility.