A 10-BIT 5MS/S LOW-VOLTAGE PIPELINE ADC
碩士 === 大同大學 === 電機工程研究所 === 94 === In this thesis, we design a 10-bits 5 Msample/s low-voltage pipeline ADC. Because the threshold voltage of transistors does not scale with the technology, circuits used in the pipeline ADC in the past could not obtain the desired dynamic range in low voltage. Sever...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2006
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/45741108962271869327 |
| Summary: | 碩士 === 大同大學 === 電機工程研究所 === 94 === In this thesis, we design a 10-bits 5 Msample/s low-voltage pipeline ADC. Because the threshold voltage of transistors does not scale with the technology, circuits used in the pipeline ADC in the past could not obtain the desired dynamic range in low voltage. Several solutions have been proposed to overcome the problem. In this thesis, the pipeline ADC is design by opamp-reset switching technique. In addition, the comparison between different solutions has been made. We also analyze the operational amplifier requirement to meet the necessary accuracy.
|
|---|