Packet-Based Shared Link Architecture Design for Network on Chip

• Main Authors: Pin-Zhang Huang, 黃品璋
• Other Authors: Ming-Hwa Sheu
• Format: Others
• Language: zh-TW
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/54461761472925465833

碩士 === 國立雲林科技大學 === 電子與資訊工程研究所 === 94 === In this paper, we propose a new transmission interface design which is different from the shared-bus of SoC (System-on-Chip) interconnection in the past. In order to achieve the data throughput requirement and to address anticipated problems in the future SoC field, we use the concept of internetwork transmission control protocol. Data is assembled in packets by the transmission interface and is transferred in serial by LVDS (Low Voltage Differential Signaling) interface that not only increases the data throughput but also reduces the problems of data skew, interference and wire routing. The transmission interface was divided into 2 layers－Transaction Layer and Physical Layer from top to bottom. Every layer has its functions, such as packet assembly and disassembly, transmission protocol control or signal transfer. Here transmission protocol control includes Flow Control, Error Detection, Packet acknowledgement and Packet Retry. These mechanisms ensure the validity of packets when they were transmitted by high speed transmission link. Furthermore, we separate the packet into 2 types, one for transmitting data and the other for protocol control, using 2 or more transmission links to transmit these packets to achieve the requirement of throughput. The operation frequency of transmission interface in TSMC 0.13 μm process exceeds 250 Mhz, sufficient for a 10 Gbps LVDS channel.