| Summary: | 碩士 === 國立中正大學 === 資訊工程所 === 95 === Recently, following with the high power density microprocessor, the cost on cooling hardware is also increasing. The temperature-aware technique is therefore playing the important role. By running the benchmark on processor, we observe that besides the register file the temperature of cache is higher than other on-chip components. In order to reduce the cache temperature, we proposed a compiler-directed instruction scheduling technique to assemble data access on multiple-bank cache architecture and insert power hint to turn off the cache bank. We first determine that if the loop iteration could cause the unbalanced temperature of banked cache. Then calculate the locality of data on bank, and unroll the loop with instruction rescheduling. In the end, we get good result of our algorithm.
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