An Efficient Architecture for H.264 Video Decoder

• Main Authors: Chien-Chang Lin, 林建璋
• Other Authors: Jiun-In Guo
• Format: Others
• Language: en_US
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/34561601608146236134

博士 === 國立中正大學 === 資訊工程所 === 95 === In this dissertation, a low cost H.264/AVC video decoder design for high definition television (HDTV) applications is presented. The proposed design is compatible to ISO/IEC-14496-10 Baseline Profile (BP), Main Profile (MP), and High Profile (HP) video coding standard. This proposed design consists of hardware IP decoder and the associated firmware. In the architecture of the hardware IP decoder, the hybrid block mode processing is proposed to simplify the overall decoding flow and lower down the memory bandwidth. In addition, the Intra/Inter prediction and de-blocking filter modules are optimized to decrease the complexity and power consumption. In the firmware design, we modify the H.264 reference software JM as the IP firmware of the proposed design. To ensure robust functionality, over 150 test sequences including the conformance bitstreams proposed by JVT are used to verify the proposed design. Moreover, we adopt an ARM-based FPGA platform, called FIE-8100, to perform the FPGA verification of the proposed design. For fitting various applications, we have developed two design examples of the H.264 video decoder, one is the H.264 BP video decoder covering MP tools (denoted as BP/MP decoder), and the other is the H.264 HP video decoder. Through optimization from algorithmic and architectural perspectives, the proposed H.264 BP/MP decoder can achieve real-time H.264 video decoding on HD1080 video (1920x1088@30Hz) when operating at 120MHz with 320mW power dissipation. Fabricated by using the TSMC 1P6M 0.18um CMOS technology, the proposed design occupies 2.9 x 2.9 mm2 silicon area with the hardware complexity of 160K gates and 4.5K bytes of local memory. The proposed H.264 HP video decoder costs 280K gates and 7.5K bytes local memory to support HD1080i (1920x1088@30Hz) when operating at 125MHz by using TSMC 1P6M 0.18um CMOS technology.