A Sharable Cache Partitioning Algorithmfor CMP and SMT Processors
碩士 === 國立中正大學 === 資訊工程所 === 95 === Simultaneous multithreading (SMT) and chip-multiprocessor (CMP) are cur- rently two important trends in the design of processors. As two or more programs are executed in a processor, these technologies are performed good throughput in most of the cases. Recently st...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/73235197757044648984 |
| Summary: | 碩士 === 國立中正大學 === 資訊工程所 === 95 === Simultaneous multithreading (SMT) and chip-multiprocessor (CMP) are cur-
rently two important trends in the design of processors. As two or more programs
are executed in a processor, these technologies are performed good throughput in
most of the cases.
Recently studies have been shown that some programs executed in a processor
simultaneously may result in terrible throughput. And the reason happened above
is the programs compete for cache space with each other. This makes it more
difficult to predict the worst case computation time (WCET), and might even lead
to an overall low efficiency in certain circumstances. Even though the traditional
cache partitioning method can solve the foregoing two problems, it reduces the
utility rate of the cache as well as the performance of the processor.
The method presented in this paper allows the processors to share the cache
without affecting each other. Our method could virtually enlarge the cache size
and increase the level of cache set associativity. Overall, the method improve hit
ratio by more than 4% and IPC by more than 2% across the SPEC2000 benchmark
suite.
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