| Summary: | 碩士 === 長庚大學 === 電子工程研究所 === 95 === Abstract
This thesis presents the development of low-power UWB transmitter and receiver circuit with standard CMOS technology. In the transmitter, a low-power all-digital UWB pulse generator with modulator is presented. The modulated pulse is further shaped by a Chebyshev band pass filter and meets the FCC UWB frequency band (3.1-10.6 GHz) spectral mask specification. In the receiver, the received signal is demodulated to the main signal by multiplying with the signal from differential pulse generator. The demodulated signal is sent to the VGA and then into an OTA-C integrator. Finally, it is sent to the comparator to recovery the transmitted data.
The circuits are simulated by Advanced Design System (ADS) and HSPICE , fabricated by TSMC 0.18µm 1P6M CMOS process. The power consumption of the transmitter is 0.541mW, and the pulse width is 1.1ns in simulations. The baseband frequency is 200MHz. The die size is 1.4 x 1.2 mm2. The proposed Low Noise Amplifier for 3.1-10.6 GHz UWB system here is biased by the current of 6.72mA，a minimum NF of 4.8 dB, a power gain of 12 dB, better than -10 dB of input matching, and an input IP3 of -15 dBm, while consuming only 15.552 mW of power. Simulation shows that the receiver can achieve a demodulation rate of 80/200 Mbps and power consumption is 92mW. The VGA gain is 9.8dB. The gm of the OTA-C integrator is 5mS. The measurement data of transmitter is good agreement with simulation results.
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