| Summary: | 碩士 === 中原大學 === 資訊工程研究所 === 95 === In the period of Deep Submicron Technology, the functions of portable electronic products are getting more and more complex, and the power consumption of the chips is also highly increased. Therefore, it’s a very important issue to reduce the power consumption of the chips in the modern VLSI designs. Using dual supply voltages on VLSI designs is an efficient method to reduce power consumption and maintain the circuit performance. In this paper, we proposed a voltage scaling, voltage island generation algorithm in the floorplanning stage to reduce power consumption and the requirement of power-network resource by using dual supply voltage.
Our algorithm includes the following four stages: (1) Cluster the standard cells according to the connectivity and the slack. Floorplan the clusters to minimize the number of standard cells with negative slack and white space. (2) Assign the supply voltage of the standard cells with negative slack to high supply voltage. Use voltage scaling refinement under timing constraint to reduce power consumption. We reassign the supply voltage of the standard cells with high supply voltage according to their power gain. (3) Divide each mixed cluster which contains high supply voltage cells and low supply voltage cells into two single supply voltage clusters which contain only high supply voltage cells or low supply voltage cells under the timing constraint. (4) Use the floorplan refinement to minimize the requirement of power-network resource and the white space. We tested four ISCAS benchmarks, and the experimental results show that our algorithm is very effective in reducing the power consumption and the requirement of power-network resource. On average, our algorithm reduces the power consumption by 47.3%. And the average white space compared to the total area of floorplan layout is about 4.09%.
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