Design of a 64-bit Versatile Cost-Effective Hybrid Floating-Point/LNS Arithmetic Processor
碩士 === 逢甲大學 === 資訊工程所 === 95 === In this research we proposed a 64-bit hybrid Floating-Point/LNS arithmetic processor based on a 32-bit hybrid Floating-Point/LNS arithmetic processor, and our research goal is to improve its performance and reduce its hardware cost. This hybrid FLP/LNS processor can...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/14050223543464692132 |