Arbiter Design And Implementation on Multi-Layer Bus Architecture
碩士 === 義守大學 === 電子工程學系碩士班 === 95 === This thesis is aimed at developing the performance analysis and implementation of an arbiter with a hybrid arbitration algorithm. The hybrid arbitration algorithms include static fixed priority, round robin, first come first service, and random access algorithms....
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| Format: | Others |
| Language: | zh-TW |
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2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/60587684538871313005 |
| Summary: | 碩士 === 義守大學 === 電子工程學系碩士班 === 95 === This thesis is aimed at developing the performance analysis and implementation of an arbiter with a hybrid arbitration algorithm. The hybrid arbitration algorithms include static fixed priority, round robin, first come first service, and random access algorithms. In addition, the design of the reconfigurable controller is proposed in order to easily modify the configuration of the arbiter. A proposed hybrid arbitration scheme for Multi-layer bus architecture is also presented in this thesis. The research results not only provide performance analysis for the various combinations of the arbitration algorithms. The performance results can also be feed into the reconfigurable controller of the arbiter to obtain the optimal condition under different system workloads. The reconfigurable arbiter was implemented by FPGA and synthesized by Synopsys Design Complier with a TSMC 0.18 cell library.
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