| Summary: | 碩士 === 崑山科技大學 === 電子工程研究所 === 95 === In this thesis, we have been designed and finished Ultra-wideband low voltage low-noise amplifier by TSMC 0.18-μm CMOS process. Also, make use of EM analysis considering parasitical effect to reach more precisely circuit design. Then we through National Chip Implementation Center (CIC ) of the chip fabrication and on-wafer measure finally, in this thesis has two kids of circuit topology.
In first chip, the main topology is employing only one-stage cascoded amplifier and an additional voltage-current feedback. The measurement results show the following performances: maximum power gain of 9.18dB, ±0.9 dB and less than ±0.58 dB gain flatness for 3.1 - 10.6 GHz full band and single band group, minimum noise figure of 4.1dB, the IIP3 of 7.25 dBm and the P1dB of -2.5 dBm. The total power consumption is 23.5 mW under a 1.0 V supply voltage. The chip size is 0.78 mm2.
In second chip, the main topology is employing current reused amplifier and a classic filter and resistance feedback. The measurement results show the following performances: maximum power gain of 17.2 dB for 3.1 - 10.6 GHz, minimum noise figure of 2.29 dB, the IIP3 of -5 dBm and the P1dB of -13 dBm. The power consumption is 13.8 mW under a 1.2 V supply voltage. The chip size is 1.04mm2.
|
|---|
