A Cycle-Stealing Technique for Pipelined Instruction Decompression System for Embedded Microprocessors

碩士 === 國立高雄應用科技大學 === 電子與資訊工程研究所碩士班 === 95 === In this paper, we propose a high performance code compression and decompression system. At first, according to the branch instruction of ARM. We distinguish direct instructions and indirect instructions from instruction of ARM. Then we demarcate the bas...

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Bibliographic Details
Main Authors: Chin-Chung Tai, 戴誌中
Other Authors: Yuan-long Jeang
Format: Others
Language:en_US
Published: 2007
Online Access:http://ndltd.ncl.edu.tw/handle/82601726338967749751
Description
Summary:碩士 === 國立高雄應用科技大學 === 電子與資訊工程研究所碩士班 === 95 === In this paper, we propose a high performance code compression and decompression system. At first, according to the branch instruction of ARM. We distinguish direct instructions and indirect instructions from instruction of ARM. Then we demarcate the basic block defined in the machine code, and then calculate the appearance probability of all basic block. Then we use Huffman algorithm to compress each section, and achieve a better compression ratio. However before the processor execution, it must go through the decompression circuit to restore the machine code. So in our decompression portion, we proposed a pipeline with back-up for flushing (PBF) technique to avoid the loss of efficiency. We designed a Huffman Decoder within decompression system, and proposed a cycle –stealing technique to improve the time delay, and we designed a decompression system suit to pipeline. Because of improvement of performance, it must waste approximately 2.3% compression ratio. In experimental results, the average compression ratio is about 40%~43%.The hardware cost deceased about 35%, and faster than our previous version.