| Summary: | 碩士 === 國立成功大學 === 資訊工程學系碩博士班 === 95 === Digital still cameras (DSC) have been widely used as image input devices nowadays. Before a color image is generated, a lot of color image processes must be performed. Among these color image processes, the Color Filter Array (CFA) interpolation or demosaicking process may be the most important process. In othe words, the image quality of a DSC depends highly on the performance of the demosaicking process. In general, the demosaicking methods can be classified into two categories: lower-complexity techniques and higher-complexity techniques. The complexity of the former is very low. The latter yields visually pleasing images by utilizing more sophisticated demosaicking methods. However, the former is more suitable for many real-time applications, due to its simplicity and easy implementation in the VLSI chip. An excellent lower-complexity interpolation method is still needed when low-cost VLSI implementation is necessary. In this thesis, a low-complexity interpolation scheme that exploits both spatial and inter-channel correlations is presented. To achieve the goal of area-efficient design, we adopt the resource sharing and pipelined scheduling approaches to develop the VLSI architecture for the proposed scheme. The VLSI architecture is designed with Verilog and implemented with TSMC 0.35 cell library. Compared with the previous design, our chip achieves less hardware cost and higher clock rate.
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