Combined CAVLC Decoder with Inverse Quantizer and Transform for Compact H.264/AVC Decoding Kernels

• Main Authors: Shih-tse Wei, 魏世澤
• Other Authors: Jar-ferr Yang
• Format: Others
• Language: en_US
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/34436792691489397329

碩士 === 國立成功大學 === 電機工程學系碩博士班 === 95 === A low cost and efficient architecture for decoding the residual data in the H.264/AVC is proposed in this thesis. The required components consist of CAVLC decoder, inverse quantizer, and inverse transform. Since the decoding speed of these components is varied, the interface should be designed carefully to buffer the data among them. To efficiently realize the interface of the CAVLC decoder and inverse quantizer, the residual decoding procedure in the H.264/AVC is first analyzed. After the proper arrangement of the CAVLC decoding and inverse quantization procedures, the proposed architecture requires only one inverse quantizer which is further combined into the CAVLC decoder to reduce the buffer size. Moreover, the flexible 2-D multi-transform architecture which including the 4 4 inverse integer transform, 4 4 inverse Hadamard transform, and 2 2 inverse Hadamard transform is also proposed. Simulation results show that the total implemented gate counts is 14.1 k and the maximum operation frequency is 130 MHz in the proposed design. It can support the real-time requirement for the 4VGA @30 fps video resolution in 4:2:0 formats.