Design of 10-Bit Pipelined Analog-to-Digital Converter

• Main Authors: Kao, You-De, 高有德
• Other Authors: Sheu, Meng-Lieh
• Format: Others
• Language: zh-TW
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/87214225695648168808

碩士 === 國立暨南國際大學 === 電機工程學系 === 95 === Recently, as portable multimedia develops rapidly, the low power issue for analog design is more and more important. However, with the advance of the deep submicron technique, for the analog design, we faces some problems that the decreases of signal dynamic range and dynamic performance, if we want to enhance the performance to suppress the noise and distortion which suffers from nonlinearity, we will make so large current that the low power design has a challenge. In this thesis, we design a 10-bit 66.6MS/s pipelined Analog-to-Digital converter with TSMC 0.18μm CMOS 1P6M process at 1.8V supply, and adopt eight conversion stages which 1.5-bit per stage has low noise and low power dissipation advantages, there are all 9 stages. We use the modified op-amp architecture for S/H and MDAC circuit, and take four kind of different specifications for low power design. Simultaneously, for the switch design, we reduce the nonlinearity of the switch by using the voltage-bootstrapped circuit. Finally, we can get accurate 10-bit digital codes by using digital error correction circuit, which can reduce the demand of the comparator and let it tolerate ±125mv of offset voltage. In this design result, when input signal frequency at 1MHz, we get SFDR/SNR/SNDR is 58.81dB/55.62dB/51.85dB, the effective number of bit(ENOB) is 8.32bit, total power dissipation is76.36mW, and total chip area is 1mm2.