| Summary: | 碩士 === 國立暨南國際大學 === 電機工程學系 === 95 === CMOS technology is popularly used in the high frequency application. But it has some drawback to solve, like Si substrae loss, low Ft, and low Fmax. The goal of this thesis is implementation of Ku-band Phase-Locked Loop (PLL) using LC-tank Voltage-Controlled Oscillator (VCO) and Injection-Locked Frequency Divider (ILFD) in the standard CMOS technology. This thesis is divided into three parts. The first part is chapter 2, in which the most important part VCO in the PLL is presented. Chapter 3 and chapter 4 constitute the second part and present the circuits using injection-locked structure, called Superharmonic coupling quadrature VCO and ILFD. Finally, chapter 5 presents the concept and design issues of the PLL.
In the chapter 1, I introduce the motivation and state of play. And the role is played by PLL in the transceiver.
VCO is the highest frequency block of this thesis, it also the most challenging task in this system. Chapter 2 presents the LC tank, negative resistance, analysis of phase noise, and power consumption concepts. Finally, a Ku-band VCO with 28.8mW power consumption from a 1.8-V supply voltage is implemented in TSMC 0.18μm technology. Its phase noise performance is -99dBc/Hz at 1MHz offset.
Superharmonic coupling quadrature VCO produces quadrature signals by injecting anti-phase into two different VCOs. Chapter 3 introduces the principle of quadrature signals which are generated by transformer coupling. Finally, a quadrature VCO with 36.54mW power consumption from a 1.8-V supply voltage is implemented in TSMC 0.18μm technology. Its phase noise performance is -114dBc/Hz at 1MHz offset.
ILFD can be implemented easily in the high frequency with low power consumption. So it is usually incorporated in high frequency PLL. The chapter 4 introduces the principle of injection-locked explicitly, locking range, and the effect on phase noise. Finally, a Ka-band ILFD measured locking range is 1.2GHz (4.54%) from 25.8 GHz to 27 GHz with Vin=0dBm and Vtune=1.8 V. Its power consumption is 8.07mW from a 1.5V supply voltage 5.38mA core current.
In the chapter 5, a Ku band PLL be implemented using an ILFD. We introduce the principle of PLL and describe every blocks. First we implement the VCO and ILFD of PLL. Phase noise of open loop VCO in the PLL is -110dBc/Hz at 1MHz offset. The total power of VCO and ILFD is 7.336mW. And the locking range 500MHz is acceptable for PLL system. Although the PLL can not be locked eventually, we still complete the flow from design to measurement.
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