Design of Low Parasitic Capacitance and Low-power CMOS Capacitive Fingerprint Sensor Readout Circuit

• Main Authors: Yuan-Chang Huang, 黃元展
• Other Authors: Meng-Lieh Sheu
• Format: Others
• Language: zh-TW
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/57098743869355063891

碩士 === 國立暨南國際大學 === 電機工程學系 === 95 === In recent years, Biometric Identification has become the most popular research topic, and one of the most robust methods is fingerprint identification. A capacitive fingerprint sensor acquires the fingerprint image by measuring capacitance variation, caused by different distance between sensing electrode and fingerprint surface. In this thesis, we present a low parasitic capacitance and low-power CMOS Capacitive Fingerprint Sensor Readout Circuit. The effect of parasitic capacitance has been eliminated with novel layout structure in sensor cell, and minimal size switch is used in readout circuit to avoid non-ideal effect of MOS switch and to achieve good C-V characteristic. Power consumption is reduced with quiescent current control in buffer amplifier of readout circuit. A 32x32 fingerprint sensor array is implemented in TSMC 0.35μm Mixed- Signal 2P4M CMOS technology provided by Chip Implementation Center. Including the sensor array, peripheral control circuits and analog to digital converter, the chip area is 1900μm × 2570μm. The chip works at 3.3V power supply and operates at 4MHz clock rate. Capacitance value from 0fF to 60fF can be sensed, corresponding analog output voltage is from 3.02V to 1.57V and the digital output is 6 bits. The overall power consumption is less than 5.5mW.