Fast Pseudo Tile Extraction by Tagging Blockage Borders for NEMO Gridless Router

• Main Authors: Wei-Tin Lin, 林威廷
• Other Authors: Yih-Lang Li
• Format: Others
• Language: en_US
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/01269883900548449129

碩士 === 國立交通大學 === 資訊科學與工程研究所 === 95 === This investigation develops a new multilayer implicit connection graph-based gridless router with bin system. This work retains all advantages of the previous version and improves the speed of graph construction and pseudo tile extraction. The grid-lines derived from the blockages which fall entirely outside the routing region increase the complexity of routing graph and decelerate path search. Unlike the previous work that scans all grid-lines inside the routing region for filtering out redundant grid-lines, this work generates a simplified routing graph by extracting blockages in the routing region explicitly. Furthermore, continuous space tiles are combined as a pseudo maximum horizontally or vertically stripped tile for accelerating path search. By tagging blockage on the routing graph, legality check on each tile needs little query overload such that pseudo tile extraction is about ten times faster than querying the well-known slit plus interval tree. Experimental results reveal that this new gridless router around two times faster than the previous version. General-purpose routing by this work also outperforms all multilevel gridless routers with runtimes that are approximately 3.5x to 86.8x faster.