Ultra Low Power Area Efficient All Digital Phase-Locked Loop Frequency Synthesizer
碩士 === 國立交通大學 === 電子工程系所 === 95 === A new all digital phase-locked loop (ADPLL) architecture with low power algorithm is presented in this thesis. The proposed low power search algorithm can accomplish phase lock process within 22 input clock cycles and make the hardware simple, area small. In thesi...
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| Format: | Others |
| Language: | en_US |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/84333963129857541619 |
| Summary: | 碩士 === 國立交通大學 === 電子工程系所 === 95 === A new all digital phase-locked loop (ADPLL) architecture with low power algorithm is presented in this thesis. The proposed low power search algorithm can accomplish phase lock process within 22 input clock cycles and make the hardware simple, area small. In thesis, proposed low power digitally controlled oscillator (DCO) has two types. The two types of proposed DCO make proposed ADPLL lower power. The proposed NAND latch based Phase-Frequency-Detector (PFD) can detect multi times of reference frequency .This ADPLL has characteristics of small area cost and lower power consumption.
The proposed ADPLL is simulated and implemented by TSMC 0.13um 1P8M CMOS technology. The supply voltage is 1.2v and total area is 0.0041mm2. The simulation results show that when the DCO operates at 700MHz, the jitter is 18.4ps, 1.38% (Pk-Pk) and the total power consumption of ADPLL is 0.85mW.
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