| Summary: | 碩士 === 國立交通大學 === 電子工程系所 === 95 === There are kinds of techniques of reducing power dissipation or energy dissipation announced in recently years, some of which are additive while others may conflict. How to apply these techniques efficiently on a design is not straightforward. We proposed an energy optimization design methodology to integrate these techniques in a systematic way. The main ideal of this optimization flow is that energy dissipation is independent of the operation frequency but a constant if we consider dynamic power/energy dissipation only. Only with larger capacitance or higher supply voltage, will the energy consumption increase. The reason to use larger capacitance or higher voltage is to increase the performance of the design which is often requested in the real-time system. Our optimization flow then uses power-delay product as the cost function to meet higher performance requirement for each component. Find all cost functions from all the possible techniques that can be used to increase the performance of designs in a given design space, for examples, logic synthesis, structure, architecture and voltage. Optimize individual components via the cost functions and combine all the components to build up the entire design will result the most energy-efficient design. Use a discrete cosine transform engine build up by the ASIC approach to verify efficiency of the optimization flow we proposed with the performance requirement between 250MHz to 550MHz. With TSMC 0.13�慆 1P8M CMOS cell library, our approach reduces 4.47% energy consumption in average compared with conventional design methodology which is mainly optimized for the timing constraint. The optimization flow first proposed is used to optimize the energy consumption of designs with a fixed performance requirement, while there may be varying performance requirement in real cases. The optimization flow is then modified to satisfy the varying performance requirement via using certain techniques that can be used to dynamically adjust the performance of the design. Finally, we apply the optimization flow to optimize our target DSP core. Compared the results with the conventional design methodology, our approach has 8.44% energy reduction in average. Furthermore, we use the target DSP core to construct a motion JPEG-based surveillance system to explain the varying performance requirement that processors might suffer and use the optimization flow to reduce the energy consumption for the scenario. Our approach reduces 28.84% energy dissipation of those with worst-case optimizations.
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