| Summary: | 博士 === 國立交通大學 === 電子工程系所 === 95 === Advances of video coding made an adverse impact on VLSI implementation over mobile communication systems. Those impacts mainly include area, power, and channel deterioration in the video decoding side. Therefore, this dissertation presents a low-power dual-standard video decoder to improve the area/power efficiency. It supports MPEG-2 SP@ML and H.264/AVC BL@L4 video decoding in a single chip and features a scalable architecture to reduce the required silicon area as well as power dissipation. Moreover, to combat transmission errors of video streams, this design is robust to the channel behavior for improving the subjective and objective visual quality.
Specifically, we integrate diverse algorithms of MPEG-2 and H.264/AVC to reduce silicon area. Among different standards, IDCT, deblocking filter and entropy decoder are tightly combined at algorithmic and architectural levels. Several low-power techniques are proposed. First, a domain-pipelined scalability (DPS) technique is used to optimize the pipelined structure according to the number of processing cycles. Second, bandwidth scalability is implemented via three-level memory hierarchy and line-pixel-lookahead (LPL) schemes to improve the external bandwidth and reduce the internal memory size, leading to 51% of memory power reduction compared to a conventional design. Third, a novel decoding ordering is utilized to improve the access efficiency in one macroblock. Low-power motion compensation and deblocking filter are designed to reduce the operating frequency without degrading system performance. Considering the video transmission over the mobile environments, the proposal exploits an error detection to early detect and thereby conceal corrupted macroblocks. It greatly improves the visual quality by 1dB of PSNR under the 2.7×10-3 of bit error rate. Moreover, a frame re-compression method is presented to not only lower the required memory capacity but also support error-robustness features when the corrupted portion of one frame is detected.
Finally, a test chip is fabricated in a 0.18um 1P6M CMOS process with an area of 15.21mm2 and measured via a VLSI tester. For mobile applications, H.264/AVC and MPEG-2 video decoding of quarter-common intermediate format (QCIF) sequences at 15 frames per second are achieved at 1.15MHz clock frequency with power dissipation of 125uW and 108uW respectively at 1-V supply voltage. This area-efficient, low-power and error-robust design also reveals its strong suitability for mobile communication systems.
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