Encoder and Acceleration and Implementation of H.264 Scalable Extension of H.264 Decoder on TI DSP Platform

• Main Authors: Kai-Ting Cheng, 鄭凱庭
• Other Authors: Hsueh-Ming Hang
• Format: Others
• Language: en_US
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/39528377706174943831

碩士 === 國立交通大學 === 電子工程系所 === 95 === With the advancement of the digital signal processing, real-time video transmission becomes an essential element in our daily life. In this thesis, we implement the H.264/AVC encoder and the scalable extension of H.264/AVC (H.264/AVC SVC) decoder by using a digital signal processor (DSP). The digital signal processing environment is Sundance module SMT395. The core of the DSP is the Texas Instrument’s TMS320C6416T which is a powerful signal processor with strong arithmetic operation capability. For the H.264/AVC encoder, the open source code x264 is used as the basis to build a DSP-executable program. The mode decision module is the key element being accelerated. We develop an early termination method to reduce the calculation of the dispensable modes. This saves up to 13% of the encoding time. For the DSP implementation, we start with the optimization tools provided by the TI DSP complier. We also make use of the two-level cache module on the DSP platform. This can speed-up the system by about 19 times. Furthermore, we use several DSP codes acceleration techniques including fixed-point data types, TI DSP intrinsic functions and others. Through the code modifications, we can reduce the computation by 50%. Finally, the overall system can encode up to 40 QCIF frames per second on test video sequences. For the H.264/AVC SVC decoder, we start with the MPEG reference software JSVM 5.0. The H.264/AVC SVC includes three types of scalability, namely, Temporal, Spatial and SNR scalability. For the DSP implementation, we accelerate the parts which take the most computing time in the combined scalability. These two parts are the FGS and the inter-layer prediction modules. For FGS, we refine the codes to reduce the computation redundancy. For the inter-layer prediction, we reduce the up-sampling operations for the intra texture and the residuals. In addition, we also use the acceleration techniques supported by the TI DSP. The final H.264/AVC SVC decoder can reduce the computation by 49% in the combined scalability.