Low Power Low Distortion Audio Delta-Sigma DAC

• Main Authors: Yang Chia Tai, 楊家泰
• Other Authors: Chung-Chih Hung
• Format: Others
• Language: en_US
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/39032569175767754177

碩士 === 國立交通大學 === 電信工程系所 === 95 === Audio digital-to-analog converters (DAC) have played an important role recently with the rapid growth of the minidisc players and portable audio devices. There are some main issues for a battery-operated audio system. Power dissipation affects the battery life, so it must be as low as possible. A high resolution of about 16bits is required for the DAC to meet the quality of the media. The delta-sigma D/A converters have been used extensively. It can achieve high resolution, reduce digital circuit speed, relax the requirements of the out-of-band filter, and enhance immunity to clock jitter. Using the direct charge transfer switched-capacitor technique in the multi-bit reconstruction DAC can reduce kT/C noise and element mismatch without increasing power dissipation. The data weighted averaging algorithm restrains nonlinearity caused by the mismatch of capacitors. A 15-level quantization, third-order delta-sigma DAC is presented. Its sampling rate is 44.1 kHz with 18-bit input. The main clock is 2.8224 MHz because of the 64X oversampling ratio. This DAC was implemented by TSMC 0.18um CMOS process supported by CIC.