Design and Implementation of DVB-T/H Synchronization Loop and Low Power Techniques

• Main Authors: Chi-Yao Tseng, 曾琪耀
• Other Authors: Tsung-Han Tsai
• Format: Others
• Language: en_US
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/62086872994064510914

碩士 === 國立中央大學 === 電機工程研究所 === 95 === Low power design is still an important issue of IC design; in particular, the popularizing portable electronic devices are time-limited used because of the finite energy capacity of battery. Digital Video Broadcasting for Handheld (DVB-H) introduces the time-slicing technique to decrease the power consumption of mobile receiver. In this thesis, we focus on the discussion about the register transfer level (RTL) low power design techniques. And our team designs the DVB-T/H baseband inner receiver with the low power and low area consideration in respect of architecture and system level. We utilize several low power and power aware design techniques to reduce the power consumption of our DVB-T/H baseband inner receiver. These techniques include pre-computation, clock gating, operand isolation, differential encoding, hardware sharing, time-multiplexing R/W of memory, low power arithmetic architecture and power manager. At last, we use the cell based design flow to implement our baseband inner receiver. The architecture of baseband inner receiver consists of FFT, Pre-processor (Interpolator, Derotator, elastic buffer and phase accumulator), Post-processor (Coarse Symbol Synchronization, Scattered Pilot Synchronization and Channel Estimation) and Post-FFT estimation (ICFO estimation and RCFO/SCO estimation). For the Post-FFT estimation (that is, synchronization loop), the area is reduced 51.6% and the power consumption is reduced 53.3%. Moreover, the proposed power manager reduces 3% ~ 20% power consumption according to different Guard Interval (GI) when the system is operating during the offset tracking mode.