Skew Aware Polarity Assignment in Clock Tree

碩士 === 國立清華大學 === 資訊工程學系 === 95 === In modern sequential VLSI designs, clock tree plays an important role in synchronizing different components in a chip. To reduce peak current and power/ground noises caused by clock network, assigning different signal polarities to clock buffers is proposed in pre...

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Main Authors: Kuan-Hsien Ho, 何冠賢
Other Authors: TingTing Hwang
Format: Others
Language:en_US
Published: 2007
Online Access:http://ndltd.ncl.edu.tw/handle/89429643329783773372
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spelling ndltd-TW-095NTHU53921002015-10-13T16:51:15Z http://ndltd.ncl.edu.tw/handle/89429643329783773372 Skew Aware Polarity Assignment in Clock Tree 時鐘樹上考慮時序差異極性分配 Kuan-Hsien Ho 何冠賢 碩士 國立清華大學 資訊工程學系 95 In modern sequential VLSI designs, clock tree plays an important role in synchronizing different components in a chip. To reduce peak current and power/ground noises caused by clock network, assigning different signal polarities to clock buffers is proposed in previous work. Although peak current and power/ground noises are minimized by signal polarities assignment, an assignment without timing information may increase the clock skew significantly. As a result, a timing-aware signal polarities assigning technique is necessary. In this thesis, we propose a novel signal polarities assigning technique which can not only reduce peak current and power/ground noises simultaneously but also render the clock skew in control. The experimental result shows that the clock skew produced by our algorithm is 92% of original clock skew in average while the clock skews produced by three algorithms (Partition, MST, Matching) [8] are 231%, 265%, and 276%, respectively. Moreover, our algorithm is as efficient as the three algorithms of [8] in reducing peak current and power/ground noises. TingTing Hwang 黃婷婷 2007 學位論文 ; thesis 38 en_US
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language en_US
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description 碩士 === 國立清華大學 === 資訊工程學系 === 95 === In modern sequential VLSI designs, clock tree plays an important role in synchronizing different components in a chip. To reduce peak current and power/ground noises caused by clock network, assigning different signal polarities to clock buffers is proposed in previous work. Although peak current and power/ground noises are minimized by signal polarities assignment, an assignment without timing information may increase the clock skew significantly. As a result, a timing-aware signal polarities assigning technique is necessary. In this thesis, we propose a novel signal polarities assigning technique which can not only reduce peak current and power/ground noises simultaneously but also render the clock skew in control. The experimental result shows that the clock skew produced by our algorithm is 92% of original clock skew in average while the clock skews produced by three algorithms (Partition, MST, Matching) [8] are 231%, 265%, and 276%, respectively. Moreover, our algorithm is as efficient as the three algorithms of [8] in reducing peak current and power/ground noises.
author2 TingTing Hwang
author_facet TingTing Hwang
Kuan-Hsien Ho
何冠賢
author Kuan-Hsien Ho
何冠賢
spellingShingle Kuan-Hsien Ho
何冠賢
Skew Aware Polarity Assignment in Clock Tree
author_sort Kuan-Hsien Ho
title Skew Aware Polarity Assignment in Clock Tree
title_short Skew Aware Polarity Assignment in Clock Tree
title_full Skew Aware Polarity Assignment in Clock Tree
title_fullStr Skew Aware Polarity Assignment in Clock Tree
title_full_unstemmed Skew Aware Polarity Assignment in Clock Tree
title_sort skew aware polarity assignment in clock tree
publishDate 2007
url http://ndltd.ncl.edu.tw/handle/89429643329783773372
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