Design of a Power-Aware AES Cipher

• Main Authors: Zheng-Hao Shen, 沈政昊
• Other Authors: Chih-Tsun Huang
• Format: Others
• Language: zh-TW
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/47353644881834307521

碩士 === 國立清華大學 === 資訊工程學系 === 95 === The rapid increasing demand of widespread wireless, multimedia, and data networking applications has led an urgent need of the robust secure mechanism. Data security therefore plays a more and more important role for the critical communication system. Because of the heterogeneity of the applications, a large variety of the security ciphers with high throughput, small area and cost, and flexibility and scalability is required. For the portable devices, additionally, energy efficiency is the most crucial. Therefore the power-aware design methodology is expected to minimize the power consumption with the fulfillment of the performance requirement. A power-aware system is not only a conventional low-power design, but also a design that can adaptively adjust its power consumption to meet specific conditions, such as different throughput requirements, operation modes, user preferences, and operating environments. In this thesis, we present a power-aware AES cipher design. In addition to the design and implement of a high-throughput full featured AES cipher core, a power-aware architecture is proposed. The power-aware architecture consists of a power management controller to monitor and control the different power modes of the AES core, and an interface wrapper to manipulate the data transaction between multiple power/frequency domains dynamically. With the measured characteristics from our AES test chip, we analyze and discuss the performance and limitation using the proposed asynchronous interface wrapper. The experimental results show that our AES cipher proves a high performance with rich features, and the proposed power-aware architecture and methodology can further extend its energy efficiency for a wide range of security applications.