| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 95 === In this thesis, standard specification study, functional simulation, architecture design and circuit design along with FPGA implementation of multiple-point FFT, multiple constellations, and multiple guard interval ratio is presented.
Several receiving techniques are discussed, including synchronization, CFO compensation, and SFO compensation. Based on these receiving techniques, a mobile receiver architecture with low complexity and high performance is proposed. The key point of proposed receiver is the mobile equalizer. The proposed equalizer architecture is implemented by a second order regression interpolater. The key idea is to find a quadratic curve according to the channel information now. This interpolater is divided into two parts called the acquisition of interpolation coefficients and the channel response generation. To enhance the reliability of channel information, the new channel response is predicted by linear extension of old channel information.
Simulations are based on the F1 channel, P1 channel, and mobile TU6 channel with white noise. The mobile TU6 channel is based on the Jakes Doppler spectrum. Simulations are under static channels and dynamic channels.
To minimum the area of the proposed receiver, the FFT is implemented in mixed-radix based on 16-point FFT. The proposed receiver is implemented with synthesizable Verilog RTL codes by FPGA design flow. The receiver is implemented in Xilinx Virtex4 XC4VLX60. The clock operates at 36.57 MHz normally. This circuit can support 2k-, 4k-, and 8k-point FFT.
After implementation of the circuit, several enhancements are also proposed such as ICI cancelation and hardware sharing. These provide the direction to implement a more
excellent DVB-T/H receiver in the future.
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