Design and Implementation of a DVB-T/H Baseband Receiver for Mobile Reception

碩士 === 國立清華大學 === 電機工程學系 === 95 === In this thesis, standard specification study, functional simulation, architecture design and circuit design along with FPGA implementation of multiple-point FFT, multiple constellations, and multiple guard interval ratio is presented. Several receiving techniqu...

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Main Authors: Ruei-Dar Fang, 方瑞達
Other Authors: Hsi-Pin Ma
Format: Others
Language:en_US
Published: 2006
Online Access:http://ndltd.ncl.edu.tw/handle/82116018712449876219
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spelling ndltd-TW-095NTHU54420102016-05-25T04:13:40Z http://ndltd.ncl.edu.tw/handle/82116018712449876219 Design and Implementation of a DVB-T/H Baseband Receiver for Mobile Reception DVB-T/H行動基頻接收機之設計與實現 Ruei-Dar Fang 方瑞達 碩士 國立清華大學 電機工程學系 95 In this thesis, standard specification study, functional simulation, architecture design and circuit design along with FPGA implementation of multiple-point FFT, multiple constellations, and multiple guard interval ratio is presented. Several receiving techniques are discussed, including synchronization, CFO compensation, and SFO compensation. Based on these receiving techniques, a mobile receiver architecture with low complexity and high performance is proposed. The key point of proposed receiver is the mobile equalizer. The proposed equalizer architecture is implemented by a second order regression interpolater. The key idea is to find a quadratic curve according to the channel information now. This interpolater is divided into two parts called the acquisition of interpolation coefficients and the channel response generation. To enhance the reliability of channel information, the new channel response is predicted by linear extension of old channel information. Simulations are based on the F1 channel, P1 channel, and mobile TU6 channel with white noise. The mobile TU6 channel is based on the Jakes Doppler spectrum. Simulations are under static channels and dynamic channels. To minimum the area of the proposed receiver, the FFT is implemented in mixed-radix based on 16-point FFT. The proposed receiver is implemented with synthesizable Verilog RTL codes by FPGA design flow. The receiver is implemented in Xilinx Virtex4 XC4VLX60. The clock operates at 36.57 MHz normally. This circuit can support 2k-, 4k-, and 8k-point FFT. After implementation of the circuit, several enhancements are also proposed such as ICI cancelation and hardware sharing. These provide the direction to implement a more excellent DVB-T/H receiver in the future. Hsi-Pin Ma 馬席彬 2006 學位論文 ; thesis 117 en_US
collection NDLTD
language en_US
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description 碩士 === 國立清華大學 === 電機工程學系 === 95 === In this thesis, standard specification study, functional simulation, architecture design and circuit design along with FPGA implementation of multiple-point FFT, multiple constellations, and multiple guard interval ratio is presented. Several receiving techniques are discussed, including synchronization, CFO compensation, and SFO compensation. Based on these receiving techniques, a mobile receiver architecture with low complexity and high performance is proposed. The key point of proposed receiver is the mobile equalizer. The proposed equalizer architecture is implemented by a second order regression interpolater. The key idea is to find a quadratic curve according to the channel information now. This interpolater is divided into two parts called the acquisition of interpolation coefficients and the channel response generation. To enhance the reliability of channel information, the new channel response is predicted by linear extension of old channel information. Simulations are based on the F1 channel, P1 channel, and mobile TU6 channel with white noise. The mobile TU6 channel is based on the Jakes Doppler spectrum. Simulations are under static channels and dynamic channels. To minimum the area of the proposed receiver, the FFT is implemented in mixed-radix based on 16-point FFT. The proposed receiver is implemented with synthesizable Verilog RTL codes by FPGA design flow. The receiver is implemented in Xilinx Virtex4 XC4VLX60. The clock operates at 36.57 MHz normally. This circuit can support 2k-, 4k-, and 8k-point FFT. After implementation of the circuit, several enhancements are also proposed such as ICI cancelation and hardware sharing. These provide the direction to implement a more excellent DVB-T/H receiver in the future.
author2 Hsi-Pin Ma
author_facet Hsi-Pin Ma
Ruei-Dar Fang
方瑞達
author Ruei-Dar Fang
方瑞達
spellingShingle Ruei-Dar Fang
方瑞達
Design and Implementation of a DVB-T/H Baseband Receiver for Mobile Reception
author_sort Ruei-Dar Fang
title Design and Implementation of a DVB-T/H Baseband Receiver for Mobile Reception
title_short Design and Implementation of a DVB-T/H Baseband Receiver for Mobile Reception
title_full Design and Implementation of a DVB-T/H Baseband Receiver for Mobile Reception
title_fullStr Design and Implementation of a DVB-T/H Baseband Receiver for Mobile Reception
title_full_unstemmed Design and Implementation of a DVB-T/H Baseband Receiver for Mobile Reception
title_sort design and implementation of a dvb-t/h baseband receiver for mobile reception
publishDate 2006
url http://ndltd.ncl.edu.tw/handle/82116018712449876219
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