A Digitally-Calibrated 65GHz Phase-Locked Loop

• Main Authors: Jia-Hao Wu, 吳家豪
• Other Authors: 劉深淵
• Format: Others
• Language: en_US
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/83693391244474606014

碩士 === 國立臺灣大學 === 電子工程學研究所 === 95 === With the development and progress of CMOS process, the high-speed circuits should be realized by BJT in the past are gradually replaced by CMOS. In short channel communications, the demand for the high-speed circuits is higher and higher, especially the unlicensed band, 57GHz to 64GHz, which attracts more and more research. In high-speed circuits, passive inductors are frequently used, but the accuracy of those devices is still a problem. Take PLLs for example, if estimated inductance is too much or less, and with the process variation, it will lead to the non-overlap between VCO and divider and the incorrect feedback signal and the loop will fail to lock. The basic method to solve this problem is to widen the locking-range of divider. This thesis will propose some architecture to enhance the locking-range. It will derive the relation between the locking-range and injected-current in this thesis. The larger the injected-current is, the wider the locking-range is. But it often loses some current due to the parasitic capacitors. Therefore, the purpose of the first proposed architecture is to reduce leakage current based on inductors resonating with capacitors. The second and third architecture are adding extra current in order to compensate the loss of leakage current. In addition to improvement for the locking-range, we also propose a multi-band divider which can be applied to 40GHz and 60GHz systems at the same time. Traditionally, it needs to switch capacitors or inductors to achieve such wide frequency band. It not only occupies large chip area but also too much capacitor may cause the divider fail to work. In this thesis, we propose a method to integrate many inductors together and we can switch different frequency bands only with one inductor area. It has been mentioned what problems high-speed PLLs might face previously. In this thesis we propose a PLL based on the binary-search scheme. The characteristic of this PLL is to use a digital circuit to automatically search the needed frequency band, which is derived from switching capacitors. Besides, the output frequency is doubled by the frequency doubler, which lets the VCO and divider only designed at 30GHz to reduce the inaccuracy of the inductor model at too high frequency. Finally, this PLL successfully locks at the range from 64.33GHz to 66.22GHz.