Hardware Architecture of Tree Structure for Real-time Progressive Sequential Pattern Mining

• Main Authors: Bo-Han Chen, 陳伯翰
• Other Authors: Ming-Syan Chen
• Format: Others
• Language: en_US
• Online Access: http://ndltd.ncl.edu.tw/handle/00023364342740474032

碩士 === 國立臺灣大學 === 電機工程學研究所 === 95 === Traditional sequential pattern mining algorithms induce a significant amount of time. It is even worse on progressive database. In this paper, we design a hardware architecture to implement an efficient progressive sequential pattern mining algorithm. Our algorithm, HATS, uses a tree to maintain potential candidate sequential patterns in each sequence parallelly. With the pipeline design, HATS can generate candidate itemsets efficiently. We use software-hardware co-design technique on FPGA to design and verify our architecture. Our experimental result shows that HATS not only significantly outperforms competitive algorithms on synthetic datasets but also performs well on a real wireless gateway data. By processing wireless gateway log, the result of progressive sequential patterns mining provides a precise prefetching rule on wireless gateway, and minimizes the latency of mobile device query in a revolutionary way. Our design can also be adopted by other real-time applications of progressive sequential patterns mining.