| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 95 === In this thesis, we study the implementation of a two-level lossless data compression architecture that combines the PD-LZW algorithm and an approximated adaptive Huffman algorithm. In the first level, we replace most of CAM dictionaries by SRAMs in order to reduce hardware resource; in the second level, an ordered list implemented by two SRAMs is used to simulate the tree-based adaptive Huffman algorithm. Hardware architecture in compression and decompression can also share a 112-byte CAM memory, a 1048-byte SRAM and a 29-byte ROM.
To demonstrate our proposed architecture, the design has been realized by using FPGA and a cell-based library. In the FPGA part, it takes 4165 LUTs and operates at the internal working frequency of 68 MHz. In the cell-based part, the resulting chip occupies 2.9 × 2.9 mm2 and dissipates 394 mW in compression operation, 333 mW in decompression operation. Throughput in compression and decompression is between 266 Mbits/sec and 1.3 Gbits/sec.
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